1. Field of the Invention
The present invention relates to a method of manufacturing a cell transistor, and more particularly to a method of manufacturing a cell transistor which can achieve an improvement in a short-channel effect of a cell transistor as well as an improvement in a refresh characteristic of the transistor, and can also prevent a reduction in the threshold voltage of the transistor, in relation to DRAM memory cells with high integration.
2. Description of the Related Art
Under current reduction in design rule of semiconductor devices caused by the high integration density of DRAM memory cells, cell transistors are increasingly reduced in size and channel length. Such a reduced channel length exacerbates a short-channel effect of the transistors, thereby causing a reduced threshold voltage and a deterioration in a refresh characteristic of the DRAM memory cells.
Recently, in order to solve the above problem, a transistor having a recess gate has been studied.
Considering a conventional method of manufacturing the transistor having a recess gate, first, a device isolation region is formed on a silicon substrate where in the substrate is separated into an active region and device isolation region. Then, a mask, which defines a gate forming region, is formed on the substrate in the active region. By using the mask as an etching mask, the silicon substrate is etched by a predetermined thickness to form trenches. After etching completion, a general gate forming process is performed on the trenches of the substrate, thereby achieving a gate pattern. Here, the gate pattern comprises a gate oxide film, a gate electrode, and a hard mask. In order to protect the resulting gate pattern from certain subsequent processes, such as etching and washing processes, finally, insulating spacers are formed at side walls of the gate pattern.
As stated above, in the transistor having the recess gate manufactured according to the prior art, as a result of forming the trenches having a predetermined depth in the silicon substrate to be located in the gate forming region of the active region, there is achieved a channel lengthened along the profile of the trenches, thereby minimizing the generation of a short-channel effect due to the high integration of a semiconductor device.
However, the above described trench forming manner has a difficulty since the etching of the trenches must be selectively performed on a specific portion corresponding to the gate forming region among the active region of the silicon substrate without damage to the device isolation region, which divide the silicon substrate into the device separating region and the active region. As a result, a pointed silicon protrusion is formed on the substrate adjacent to the device isolation region. The silicon protrusion expands an electric field, resulting in a deterioration in the refresh characteristic of the DRAM memory cells.